CDRE0=0, INV=0, IOCE=0, NFEN=0, OSTPE=0, IOCF=0, CDRE2=0, CDRE1=0, CDRE3=0, ST=0, SSF=0, PIDF=0, NFCS=00, PIDE=0, OSTPF=0
POEG Group D Setting Register
| PIDF | Port Input Detection Flag 0 (0): The selected input level was not detected on the GTETRGn pin 1 (1): The selected input level was detected on the GTETRGn pin |
| IOCF | GPT or ACMPHS Output Stop Request Detection Flag 0 (0): Neither stopping of GPT output nor a comparator edge was detected 1 (1): Either stopping of GPT output or comparator edge was detected |
| OSTPF | Oscillation Stop Detection Flag 0 (0): Stopping of oscillation was not detected 1 (1): Stopping of oscillation was detected |
| SSF | Software Stop Flag 0 (0): Software has not stopped output 1 (1): Software has stopped output |
| PIDE | Port Input Detection Enable 0 (0): Detection of input levels on the corresponding GTETRGn pin is disabled 1 (1): Detection of input levels on the corresponding GTETRGn pin is enabled |
| IOCE | GPT Output Stop Request Enable 0 (0): Detection of stopping of output from the GPT is disabled 1 (1): Detection of stopping of output from the GPT is enabled |
| OSTPE | Enable Stopping Output on Stopping of Oscillation 0 (0): Detection of stopping of oscillation is disabled 1 (1): Detection of stopping of oscillation is enabled |
| CDRE0 | ACMPHS0 Enable 0 (0): Comparator edge detection 0 is disabled 1 (1): Comparator edge detection 0 is enabled |
| CDRE1 | ACMPHS1 Enable 0 (0): Comparator edge detection 1 is disabled 1 (1): Comparator edge detection 1 is enabled |
| CDRE2 | ACMPHS2 Enable 0 (0): Comparator edge detection 2 is disabled 1 (1): Comparator edge detection 2 is enabled |
| CDRE3 | ACMPHS3 Enable 0 (0): Comparator edge detection 3 is disabled 1 (1): Comparator edge detection 3 is enabled |
| ST | GTETRGn Input Status Flag 0 (0): The corresponding external trigger for output to the GPT is 0 1 (1): The corresponding external trigger for output to the GPT is 1 |
| INV | GTETRGn Input Inverting 0 (0): Input on the GTETRGn pin is not inverted 1 (1): Input on the GTETRGn pin is inverted |
| NFEN | Noise filter Enable 0 (0): Digital noise filter on the GTETRGn pin is disabled 1 (1): Digital noise filter on the GTETRGn pin is enabled |
| NFCS | Noise filter Clock Select 0 (00): Samples the input level of GTETRGn pin three times per PCLKB/1 clock 1 (01): Samples the input level of GTETRGn pin three times per PCLKB/8 clock 2 (10): Samples the input level of GTETRGn pin three times per PCLKB/32 clock 3 (11): Samples the input level of GTETRGn pin three times per PCLKB/128 clock |